`timescale 1ns/1ns
module tb_sys_init();
reg sys_clk;
reg sys_rst_n;
wire init_done;

wire [9:0] cnt;
assign cnt = sys_init_inst.cnt;

initial
begin
	sys_clk = 1'b1;
	sys_rst_n <= 1'b0;
#60
	sys_rst_n <= 1'b1;
end

always #10 sys_clk = ~sys_clk;

sys_init sys_init_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.init_done(init_done)
);

endmodule